The present invention relates to an interconnect substrate, a semiconductor device and a method of manufacturing the same, a circuit hoard, and an electronic instrument.
Multi-chip modules formed by mounting a plurality of semiconductor chips on an interposer have been known. An interconnect pattern is formed on the interposer. The interconnect pattern includes a plurality of lands for connecting a plurality of electrodes of the semiconductor chips and a plurality of lands for forming external terminals.
In the case where the lands for forming external terminals are concentrated in the region of the interposer on which one of the semiconductor chips is mounted, the interconnect pattern must be formed so as to run between the lands for connecting the electrodes of the semiconductor chip.
However, as electronic parts are mounted in higher density, there have been cases where no space is available for allowing the interconnect pattern to run between the lands. In such cases, the interconnect pattern must take a roundabout route in order to avoid the lands.
The present invention has been achieved to solve this problem. An objective of the present invention is to provide an interconnect substrate capable of preventing the interconnect length from increasing, a semiconductor device and a method of manufacturing the same, a circuit board, and an electronic instrument.
(1) An interconnect substrate according to the present invention comprises:
an upper substrate including a mounting region for a first electronic chip and an upper interconnect pattern; and
a lower substrate including a first region to which the upper substrate is adhered, a second region including amounting region for a second electronic chip, and a lower interconnect pattern,
wherein the lower interconnect pattern comprises a plurality of first lower land sections which are formed in the center portion of the first region and are electrically connected to the upper interconnect pattern, a plurality of second lower land sections which are formed in the second region and electrically connected to the second electronic chip, and a plurality of lower connection sections which run outside the center portion in the first region and connect the first lower land sections to the second lower land sections.
According to the present invention, second upper land sections electrically connected to the first electronic chip and the second lower land sections electrically connected to the second electronic chip are formed on different substrates. Therefore, it is unnecessary to form the:lower connection sections between the second upper land sections. As a result, an increase in the interconnect length can be prevented.
Since the interconnect substrate according to the present invention uses the upper substrate and the lower substrate, the interconnect substrate can be formed at low cost in comparison with built-up substrates.
In addition, since the lower connection sections run outside the first lower land sections, the lower connection sections can be formed by effectively using space on the lower substrate.
(2) In this interconnect substrate, the upper interconnect pattern may comprise a plurality of first upper land sections which are formed in the center portion of the upper substrate and are electrically connected to the first lower land sections, a plurality of second upper land sections which are electrically connected to the first electronic chip, and a plurality of upper connection sections which connect the first upper land sections to the second upper land sections.
According to this feature, since the upper connection sections only connect the first upper land sections to the second upper land sections, the upper connection sections can be formed through the shortest route.
(3) In this interconnect substrate, the lower substrate may be rectangular, the first region and the second region may be disposed side by side, one end portion of a pair of parallel end portions of the first region and one end portion of a pair of parallel end portions of the second region may be disposed along one side of a pair of parallel sides of the lower substrate, and the other end portion of a pair of parallel end portions of the first region and the other end portion of a pair of parallel end portions of the second region may be disposed along the other side of a pair of parallel sides of the lower substrate.
(4) In this interconnect substrate, the second lower land sections may be formed in a pair of parallel end portions of the second region, and the second upper land sections may be formed in a pair of parallel end portions of the upper substrate above a pair of parallel end portions of the first region of the lower substrate.
According to this feature, the second lower land sections electrically connected to the second electronic chip are formed in the end portions of the second region of the lower substrate. The second upper land sections electrically connected to the first electronic chip are formed above the, end portions of the first region of the lower substrate. The second lower land sections and the second upper land sections are formed in rows.
A plurality of electrodes of the first and second electronic chips mounted on this interconnect substrate are formed in two parallel end portions. The first and second electronic chips are mounted with the electrodes being disposed on the end portions of the upper substrate and the lower substrate.
(5) In this interconnect substrate, the second upper land sections and the second lower land sections may be formed in the same arrangement pattern, and one of the second upper land sections and one of the second lower land sections formed at the same position in each arrangement pattern may be electrically connected to the same first upper land section and the same first lower land section.
According to this feature, the same, electronic chip as the first and second electronic chips can be used.
(6) In this interconnect substrate, dummy patterns electrically insulated from the upper interconnect pattern and the lower interconnect pattern may be formed in a pair of parallel end portions of the first region of the lower substrate to the same thickness as the lower interconnect pattern.
According to this feature, the upper substrate can be supported by the dummy patterns in the case where a lower interconnect pattern is not been formed under the second upper land sections of the upper substrate, whereby the pattern can be planarized.
(7) In this interconnect substrate, an insulation film may be formed on the lower connection sections at least in the area across the first and second regions.
This prevents occurrence of short circuits between the lower connection sections.
(8) In this interconnect substrate, the upper interconnect pattern may be formed on one surface of the upper substrate, the lower interconnect pattern may be formed on one surface of the lower substrate, and the surface of the upper substrate opposite to the surface on which the upper interconnect pattern is formed may be adhered to the surface of the lower substrate. on which the lower interconnect pattern is formed.
According to this feature, the upper interconnect pattern and the lower interconnect pattern respectively formed on the upper substrate and the lower substrate are disposed facing in the same direction.
(9) In this interconnect substrate, a plurality of through-holes may be formed in the upper substrate, and the first upper land sections and the first lower land sections may be electrically connected via the through-holes.
(10) In this interconnect substrate, the first upper land sections may be formed over the through-holes, the through-holes may be located over the first lower land sections, and a conductive material in contact with the first upper land sections and the first lower land sections may be provided in the through-holes.
(11) In this interconnect substrate, a plurality of through-holes for forming a plurality of external terminals which are electrically connected to the first lower land sections and project from a surface of the lower substrate opposite to a surface on which the lower interconnect pattern is formed, may be formed in the lower substrate.
(12) In this interconnect substrate, the lower connection sections may run closer to the center than the second lower land sections in the second region.
According to this feature, since the lower connection sections run closer to the center than the second lower land sections, the lower connection sections can be formed without increasing the area of the lower substrate.
(13) In this interconnect substrate, at least one hole for electrically connecting the second lower land sections to a surface of the lower substrate opposite to a surface on which the lower interconnect pattern is formed, may be formed in the second region of the lower substrate.
(14) In this interconnect substrate, the hole may be a slit, part of the lower interconnect pattern may be formed across the slit, and the second lower land sections maybe formed over the slit.
According to this feature, the second lower land sections can be exposed to both surfaces of the lower substrate by merely forming the slits. This enables the mounting regions for the electronic chips to be formed on both surfaces of the lower substrate.
(15) An interconnect substrate according to the present invention on which electronic chips are respectively mounted in a plurality of adjacent mounting regions, the interconnect substrate comprises:
a plurality of first land sections for external connection which are formed in one of the mounting regions located at an end portion;
a plurality of second land sections which are formed in each of the mounting regions and are electrically connected to each of the electronic chips; and
a plurality of connection sections which electrically connect the second land sections respectively formed in the adjacent mounting regions,
wherein the connection sections are formed outside the second land sections in an area between the one of the mounting regions in which the first land sections are formed and another of the mounting regions adjacent to the one of the mounting regions, and
wherein the connection sections are formed inside the second land sections in an area between the mounting regions at an uneven-numbered position from the first land sections and the mountings region at an even-numbered position from the first land sections.
According to the present invention, the connection sections electrically connect the second land sections in each of the adjacent mounting regions. The connection sections formed outside the second land sections and the connection sections formed inside the second land sections are formed alternately in every mounting region. Therefore, since the connection sections do not run between the second land sections, the connection sections can be formed through the shortest route.
The connection sections are formed outside the second land sections between the mounting region in which the first land sections are formed and the mounting region adjacent thereto. Therefore, the connection sections can be formed by effectively using space. As a result, an increase in the interconnect length can be prevented.
Moreover, the interconnect substrate according to the present invention can be formed at low cost in comparison with built-up substrates.
(16) In this interconnect substrate, the second land sections may be formed outside the first land sections.
(17) In this interconnect substrate, the mounting regions may be aligned in one direction, and the second land sections may be aligned in the direction in which the mounting regions are aligned.
(18) In this interconnect substrate, the second land sections may be formed in each of the mounting regions in the same alignment pattern, and a pair of second land sections formed at a line-symmetrical position with respect to a boundary between the mounting regions may be electrically connected in the adjacent mounting regions.
According to this feature, electronic chips having a mirror-reversed structure can be mounted in the adjacent mounting regions.
(19) In this interconnect substrate, an insulation film may be formed on the connection sections at least in the area across the adjacent mounting regions.
This prevents occurrence of short circuits between the connection sections.
(20) An interconnect substrate according to the present invention comprises a first region, a second region which is formed adjacent to the first region and includes a mounting region for an electronic chip, and an interconnect pattern,
wherein the interconnect pattern comprises a plurality of first land sections formed in the first region, a plurality of second land sections which are formed in the second region and are electrically connected to the electronic chip, and a plurality of connection sections which run closer to a center than the second land sections in the second region and electrically connect the first land sections to the second land sections.
According to the present invention, the connection sections which connect the first and second land sections run closer to the center than the second land sections in the second region, thereby preventing the area of the interconnect substrate from increasing outside the second land sections. Specifically, the connection sections can be formed by effectively using space. As a result, an increase in the interconnect length can be prevented.
(21) In this interconnect substrate, the interconnect substrate may be rectangular, and pairs of parallel end sections of the first and second regions may be connected to form a pair of parallel sides of the rectangle.
(22) In this interconnect substrate, the second land sections may be formed in a pair of parallel end portions of the second region continuous with the first region.
According to this feature, the second land sections electrically connected to the electronic chip are formed in the end portions of the second region of the interconnect substrate.
A plurality of electrodes of the electronic chip mounted on this interconnect substrate is formed in two parallel end portions. The electronic chip is mounted on the interconnect substrate with the electrodes being disposed on the end portions of the interconnect substrate.
(23) In this interconnect substrate, a plurality of through-holes for forming external terminals, which are electrically connected to the first land-sections and are projected from a surface opposite to a surface on which the interconnect pattern is formed, may be formed in the first region.
(24) In this interconnect substrate, an insulation film may be formed on the connection sections at least in the area across the first and second regions.
This prevents occurrence of short circuits between the connection sections.
(25) In this interconnect substrate, at least one hole for electrically connecting the second land sections to a surface opposite to a surface on which the interconnect pattern is formed, may be formed in the second region.
(26) In this interconnect substrate, the hole may be a slit, part of the interconnect pattern may be formed across the slit, and the second land sections may be formed on the slit.
According to this feature, the second land sections can be exposed to both surfaces of the interconnect substrate by only forming the slits. This enables the mounting regions for the electronic chips to be formed on both surfaces of the interconnect substrate.
(27) A semiconductor device according to the present invention comprises the above-described interconnect substrate, a first semiconductor chip mounted in the mounting region of the upper substrate, and a second semiconductor chip mounted in the mounting region of the lower substrate.
According to the present invention, since the second upper land sections electrically connected to the first electronic chip and the second lower land sections electrically connected to the second electronic chip are formed on different substrates, the lower connection sections are not formed to run between the second upper land sections. As a result, an increase in the interconnect length can be prevented.
Since the lower connection sections run outside the first lower land sections, the lower connection sections are formed by effectively using space on the lower substrate.
(28) This semiconductor device may further comprise a third semiconductor chip electrically connected to the second lower land sections through the holes, and is mounted on a surface of the lower substrate opposite to a surface on which the second semiconductor chip is mounted.
According to this feature, since the semiconductor chips are mounted on both surfaces of the lower substrate, a high-density semiconductor device can be provided by effectively using the area of the semiconductor device.
(29) In this semiconductor device, the second and third semiconductor chips may have a mirror-symmetrical circuit structure with respect to a boundary of the lower substrate.
According to this feature, the same devices can be electrically connected to the same second lower layer land section through the shortest route.
(30) In this semiconductor device, the first and second semiconductor chips may be layered by bending the lower substrate.
This enables miniaturization of the semiconductor device.
(31) A semiconductor device according to the present invention comprises the above-described interconnect substrate, and semiconductor chips mounted in each mounting region.
According to the present invention, the connection sections electrically connect the second land sections in the adjacent mounting regions. The connection sections formed outside the second land sections and the connection sections formed inside the second land sections are formed alternately in every mounting region. Therefore, since the connection sections do not run between the second land sections, the connection sections are formed through the shortest route.
The connection sections are formed outside the second land sections between the mounting region in which the first land sections are formed and the mounting region adjacent thereto. Therefore, the connection sections are formed by effectively using space. As a result, an increase in the interconnect length can be prevented.
(32) In this semiconductor device, the semiconductor chips respectively mounted in the mounting regions may be layered by bending the interconnect substrate.
This enables miniaturization of the semiconductor device.
(33) A semiconductor device according to the present invention comprises the above-described interconnect substrate, and a first semiconductor chip mounted in the mounting region.
According to the present invention, the connection sections which connect the first and the second land sections run closer to the center than the second land sections in the second region, thereby preventing the area of the interconnect substrate from extending outside the second land sections. Specifically, the connection sections can be formed by effectively using space. As a result, an increase in the interconnect length can be prevented.
(34) This semiconductor device may further comprise a second semiconductor chip electrically connected to the second land sections through the holes, and is mounted on a surface of the lower substrate opposite to a surface on which the first semiconductor chip is mounted.
According to this feature, since the semiconductor chips are mounted on both surfaces of the interconnect substrate, a high-density semiconductor device can be provided by effectively using the area of the semiconductor device.
(35) In this semiconductor device, the first and second semiconductor chips may have a mirror-symmetrical circuit structure with respect to a boundary of the interconnect substrate.
According to this feature, the same devices can be electrically connected to the same second layer land section through the shortest route.
(36) In this semiconductor device, the first land sections may be disposed inside the mounting region by bending the interconnect substrate.
According to this feature, since the first land sections are disposed inside the mounting region, a semiconductor device having a size approximately same as the semiconductor chips can be provided.
(37) A circuit board according to the present invention is equipped with the above semiconductor device.
(38) An electronic instrument according to the present invention comprises the above semiconductor device.
(39) A method of manufacturing a semiconductor device according to the present invention comprises a step of mounting a first semiconductor chip in the mounting region of the upper substrate of the above-described interconnect substrate, and mounting a second semiconductor chip in the mounting region of the lower substrate.
According to the present invention, since the second upper land sections electrically connected to the first electronic chip and the second lower land sections electrically connected to the second electronic chip are formed on different substrates, the lower connection sections are not formed to run between the second upper land sections. As a result, an increase in the interconnect length can be prevented.
Since the lower connection sections run outside the first lower land sections, the lower connection sections are formed by effectively using space on the lower substrate.
(40) This method of manufacturing a semiconductor device may further comprise a step of mounting a third semiconductor chip on a surface of the lower substrate opposite to a surface on which the second semiconductor chip is mounted in a manner of electrically connecting the third semiconductor chip to the second lower land sections through the holes.
According to this method, since the semiconductor chips are mounted on both surfaces of the lower substrate, a high-density semiconductor device can be manufactured by effectively using the area of the semiconductor device.
(41) In this method of manufacturing a semiconductor device, the second and third semiconductor chips may have a mirror-symmetrical circuit structure with respect to a boundary of the lower substrate.
According to this feature, the same devices can be electrically connected to the same second lower layer land section through the shortest route.
(42) In this method of manufacturing a semiconductor device, the first and second semiconductor chips may be layered by bending the lower substrate.
This enables miniaturization of the semiconductor device.
(43) A method of manufacturing a semiconductor device according to the present invention comprises a step of mounting semiconductor chips respectively in the mounting regions of the above-described interconnect substrate.
According to the present invention, the connection sections electrically connect the second land sections in the adjacent mounting regions. The connection sections formed outside the second land sections and the connection sections formed inside the second land sections are formed alternately in every mounting region. Therefore, since the connection sections do not run between the second land sections, the connection sections are formed through the shortest route.
Since the connection sections are formed outside the second land sections between the mounting region in which the first land sections are formed and the mounting region adjacent thereto, the connection sections are formed by effectively using space. As a result, an increase in the interconnect length can be prevented.
(44) In this method of manufacturing a semiconductor device, the semiconductor chips respectively mounted in the mounting regions may be layered by bending the interconnect substrate.
This enables miniaturization of the semiconductor device.
(45) A method of manufacturing a semiconductor device according to the present invention comprises a step of mounting a first semiconductor chip in the mounting region of the above-described interconnect substrate.
According to the present invention, the connection sections which connect the first and the second land sections run closer to the center than the second land sections in the second region, thereby preventing the area of the interconnect substrate from extending outside the second land sections. Specifically, the connection sections can be formed by effectively using space. As a result, an increase in the interconnect length can be prevented.
(46) This method of manufacturing a semiconductor device may further comprise a step of mounting a second semiconductor chip on a surface of the interconnect substrate opposite to a surface on which the first semiconductor chip is mounted, in a manner of electrically connecting the third semiconductor chip to the second land sections through the holes.
According to this method, since the semiconductor chips are mounted on both surfaces of the interconnect substrate, a high-density semiconductor device can be manufactured by effectively using the area of the semiconductor device.
(47) In this method of manufacturing a semiconductor device, the first and second semiconductor chips may have a mirror-symmetrical circuit structure with respect to a boundary of the interconnect substrate.
According to this feature, the same devices can be electrically connected to the same second lower layer land section through the shortest route.
(48) This method of manufacturing a semiconductor device may further comprise a step of disposing the first land sections inside the mounting region by bending the interconnect substrate.
According to this method, since the first land sections are disposed inside the mounting region, a semiconductor device approximately as small as the semiconductor chips can be manufactured.